This invention relates generally to the field of electronic devices and more particularly to method for detecting the step height of shallow trench isolation structures.
Shallow trench isolation (STI) has become a main isolation method for making micro/nano-electronic circuits in recent years. Forming STI structures on a semiconductor wafer involves the use of chemical mechanical polishing (CMP). CMP is used to reduce the height of the STI structures across the wafer forming to form a planar surface with the surface of the wafer. Due to differences in the density of these STI structures across the wafer, CMP sometimes results in non-uniform reduction in the step height of the STI structures. In some instances over polishing or dishing is obtained while in other cases under polishing results in a large step height between the top of the remaining STI structure and the surface of the wafer. Processing techniques such as patterned etch back and the use of highly selective polishing slurries have helped to reduce the step height remaining after CMP. Regardless of the CMP method used it is critical that an accurate measure of the remaining step height be obtained for integrated circuit diagnostics and CMP process control. Current methods of measuring the step height include cross-section SEM/TEM and atomic force microscopy (AFM). These techniques are either destructive (SEM/TEM) or time consuming (AFM). There is therefore a need for a sensitive nondestructive method that will accurately determine the STI step height.
The instant invention is a method of determining the step height of a STI structure. The method requires fabricating a novel polysilicon sidewall structure and measuring the electrical resistance of the structure. Using the relationship between the step height and the measured resistance, the step height can be determined. A major advantage of the instant invention is that the polysilicon sidewall structure self adjusts to the step height of STI structure. This enables the formation of the polysilicon sidewall structure to be integrated into existing device process steps. No additional processing step are required.